1. Field
The present disclosure relates to wiring structures and electronic devices employing the wiring structures.
2. Description of the Related Art
In some cases, reduction in a line width or a thickness of metal wiring of high-density high-performance semiconductor devices may result in an increase in the quantity of semiconductor chips to be integrated per wafer, thereby augmenting semiconductor chip operations. In addition, a small thickness of metal wiring may reduce line capacitance, resulting in an increase in a speed of signals passing through the wiring and thereby further improving semiconductor device performance.
In some cases, wiring electrical resistance (referred to herein as simply “resistance”) may increase as the line width or the thickness of the metal wiring is reduced. As a result, reduction of the resistance in a wiring structure may enable further improvement in semiconductor device operations. In some cases, interconnect technology is approaching a physical limit where specific resistance increases as the line width and thickness of the metal wiring are reduced, to the point where the increased resistance frustrates semiconductor device operations where line width and metal wiring thickness are reduced below a threshold limit.